Digital Design of CPU and Cache Systems
Developed CPU and cache architectures using logic gates and digital design techniques.
Applied logic-based approaches to optimize memory access and data flow within the cache.
Conducted simulations to test and validate performance, ensuring reliability and functionality.
CPU Components:
1, Program Counter (PC): Tracks the current instruction address.
2, Instruction Decoder: Decodes instructions to generate control signals.
3, Register File: Stores and manages register values for operations.
Cache System:
1, 8-entry Direct Mapped Cache
2, Valid Bit: Indicates if data is loaded in the cache line.
3, Dirty Bit: Marks whether cache data has been modified.
4, TAG: Identifies cached data address.
5, Cache Data: Actual data stored within cache lines.
Database System Project: L-Store Implementation
Single-Threaded: In-memory L-Store: Built a foundational in-memory database using L-Store architecture with base/tail pages for efficient data storage; implemented SQL-like operations (INSERT, SELECT, UPDATE, DELETE). Multi-threading: Introduced concurrent processing with a thread pool and synchronization primitives to handle simultaneous transactional (OLTP) and analytical (OLAP) queries.
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# Version | Version_Tail | MIN rid range | MAX rid range
# FOR BASE PAGES
# example: 5 columns
# i += 5, for each page increment by 5 for easy book keeping
# --Indirection | --Column Pages--- |
# meta0-tail | Page 0 | Page 1 | and so on
# meta1-tail | Page 5 | Page 6 |
# meta2-tail | Page 10 | Page 11 |
# meta3-tail | Page 15 | Page 16 |
# meta4-tail | Page 20 | Page 21 |
'''